2016年4月28日 星期四

Jetson TX1 rebuild Kernel, error and solution

Thanks everyone for great instructions and links, I was able to download/install cross compilers and implement 2 workarounds: 

#(1). To Fix 'error: r7 cannot be used in asm here' problem
# add he followin
# KBUILD_CFLAGS_KERNEL := -fomit-frame-pointer
# to line 378 of makefile
#(2). To fix error "logical not is only applied to the left hand side of comparison"
# Chnage line 1065 of "tegra21_clocks.c" to:
# c->state = ((!is_lp_cluster()) == (c->u.cpu.mode == MODE_G)) ? ON : OFF;
#
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how-do-i-disable-update-apt-xapi

http://askubuntu.com/questions/488242/how-do-i-disable-update-apt-xapi
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2016年4月26日 星期二

Jetson TX1 native compile, but build error for lacking aarch64 toolchain

https://github.com/jetsonhacks/TX1FTDIModule/blob/master/installGCC.sh

compile之前，先去 /usr/src/linux-xxxx/

make modules_prepare
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2016年4月14日 星期四

Nvidia Linux driver package quick start 

NVIDIA TEGRA LINUX DRIVER PACKAGE QUICK-START GUIDE

The information here is intended to help you quickly get started using
NVIDIA Tegra Linux Driver package (L4T).

ASSUMPTIONS:

- You have an NVIDIA Jetson TX1 Developer Kit, equipped with the Jetson TX1 module.
- You have a host machine that is running Linux.
- Your developer system is cabled as follows:
  - USB Micro-A cable connecting Jetson TX1 carrier board (USB0) to your Linux host
    for flashing.
  - (Not included in the developer kit) To connect USB peripherals such as keyboard and
    mouse, a USB hub should be connected to the USB port (USB1) on the Jetson TX1
    carrier board.
- The following directions will create a 14 GB partition on the eMMC device (internal storage)
  and will flash the root file system to that location.
- If you would like to have network access on your target (e.g., for installing
  additional packages), ensure an Ethernet cable is attached to the Jetson TX1 carrier board.

INSTRUCTIONS:

1. Download the latest L4T release package for your developer system and the
   sample file system from https://developer.nvidia.com/linux-tegra

   If NVIDIA does not yet provide public release for the developer system you have,
   please contact your NVIDIA support representative to obtain the latest L4T release
   package for use with the developer board.

2. Untar the files and assemble the rootfs:

   sudo tar xpf Tegra210_Linux_R23.2.0_armhf.tbz2
   cd Linux_for_Tegra/rootfs/
   sudo tar xpf ../../Tegra_Linux_Sample-Root-Filesystem_R23.2.0_armhf.tbz2
   cd ../
   sudo ./apply_binaries.sh

3. Flash the rootfs onto the system's internal eMMC.

   a) Put your system into "reset recovery mode" by holding down the REC (S3)
      button and press the RST (S1) button once on the carrier board.
   b) Ensure your Linux host system is connected to the carrier board through the
      USB Micro-A cable.
      The flashing command is:

        sudo ./flash.sh jetson-tx1 mmcblk0p1

      This will take several minutes.

4. The target will automatically reboot upon completion of the flash. You now have Linux
   running on your developer system. Depending on the sample file system used, you will
   see one of the following on the screen:

   - The Ubuntu graphical desktop.
   - The command prompt. Log in as user login:ubuntu and  password:ubuntu.
     See step 5 if you wish to configure the graphical desktop on your setup.

5. Installing the graphical desktop on your target board (if not already installed):

   a) Connect Ethernet to target via the RJ45 connector.

   b) Acquire an IP address:

      sudo dhclient <interface>

      where <interface> is eth0.

   c) Check to see if Ethernet is up and running. You should see an IP address
      associated with eth0.

      ifconfig
      sudo apt-get update
      sudo apt-get install ubuntu-desktop

   d) Reboot and the system will boot to the graphical desktop.

   NOTE: the above steps can be used to install other packages with "sudo apt-get install".

Please refer to the release notes provided with your software for up-to-date information
on platform features and use.
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2016年4月12日 星期二

Nvidia 縮寫 

NVIDIA Tegra host1x

Required properties:
- compatible: "nvidia,tegra<chip>-host1x"
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- #address-cells: The number of cells used to represent physical base addresses
  in the host1x address space. Should be 1.
- #size-cells: The number of cells used to represent the size of an address
  range in the host1x address space. Should be 1.
- ranges: The mapping of the host1x address space to the CPU address space.
- clocks: Must contain one entry, for the module clock.
  See ../clocks/clock-bindings.txt for details.
- resets: Must contain an entry for each entry in reset-names.
  See ../reset/reset.txt for details.
- reset-names: Must include the following entries:
  - host1x

The host1x top-level node defines a number of children, each representing one
of the following host1x client modules:

- mpe: video encoder

  Required properties:
  - compatible: "nvidia,tegra<chip>-mpe"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - mpe

- vi: video input

  Required properties:
  - compatible: "nvidia,tegra<chip>-vi"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - vi

- epp: encoder pre-processor

  Required properties:
  - compatible: "nvidia,tegra<chip>-epp"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - epp

- isp: image signal processor

  Required properties:
  - compatible: "nvidia,tegra<chip>-isp"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - isp

- gr2d: 2D graphics engine

  Required properties:
  - compatible: "nvidia,tegra<chip>-gr2d"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - 2d

- gr3d: 3D graphics engine

  Required properties:
  - compatible: "nvidia,tegra<chip>-gr3d"
  - reg: Physical base address and length of the controller's registers.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    (This property may be omitted if the only clock in the list is "3d")
    - 3d
      This MUST be the first entry.
    - 3d2 (Only required on SoCs with two 3D clocks)
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - 3d
    - 3d2 (Only required on SoCs with two 3D clocks)

- dc: display controller

  Required properties:
  - compatible: "nvidia,tegra<chip>-dc"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dc
      This MUST be the first entry.
    - parent
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - dc
  - nvidia,head: The number of the display controller head. This is used to
    setup the various types of output to receive video data from the given
    head.

  Each display controller node has a child node, named "rgb", that represents
  the RGB output associated with the controller. It can take the following
  optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel

- hdmi: High Definition Multimedia Interface

  Required properties:
  - compatible: "nvidia,tegra<chip>-hdmi"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - hdmi-supply: supply for the +5V HDMI connector pin
  - vdd-supply: regulator for supply voltage
  - pll-supply: regulator for PLL
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - hdmi
      This MUST be the first entry.
    - parent
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - hdmi

  Optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel

- tvo: TV encoder output

  Required properties:
  - compatible: "nvidia,tegra<chip>-tvo"
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain one entry, for the module clock.
    See ../clocks/clock-bindings.txt for details.

- dsi: display serial interface

  Required properties:
  - compatible: "nvidia,tegra<chip>-dsi"
  - reg: Physical base address and length of the controller's registers.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dsi
      This MUST be the first entry.
    - lp
    - parent
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - dsi
  - avdd-dsi-supply: phandle of a supply that powers the DSI controller
  - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying
    which pads are used by this DSI output and need to be calibrated. See also
    ../display/tegra/nvidia,tegra114-mipi.txt.

  Optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel
  - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang
    up with in order to support up to 8 data lanes

- sor: serial output resource

  Required properties:
  - compatible: Should be:
    - "nvidia,tegra124-sor": for Tegra124 and Tegra132
    - "nvidia,tegra132-sor": for Tegra132
    - "nvidia,tegra210-sor": for Tegra210
    - "nvidia,tegra210-sor1": for Tegra210
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - sor: clock input for the SOR hardware
    - parent: input for the pixel clock
    - dp: reference clock for the SOR clock
    - safe: safe reference for the SOR clock during power up
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - sor

  Optional properties:
  - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
  - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
  - nvidia,edid: supplies a binary EDID blob
  - nvidia,panel: phandle of a display panel

  Optional properties when driving an eDP output:
  - nvidia,dpaux: phandle to a DispayPort AUX interface

- dpaux: DisplayPort AUX interface
  - compatible: For Tegra124, must contain "nvidia,tegra124-dpaux".  Otherwise,
    must contain '"nvidia,<chip>-dpaux", "nvidia,tegra124-dpaux"', where
    <chip> is tegra132.
  - reg: Physical base address and length of the controller's registers.
  - interrupts: The interrupt outputs from the controller.
  - clocks: Must contain an entry for each entry in clock-names.
    See ../clocks/clock-bindings.txt for details.
  - clock-names: Must include the following entries:
    - dpaux: clock input for the DPAUX hardware
    - parent: reference clock
  - resets: Must contain an entry for each entry in reset-names.
    See ../reset/reset.txt for details.
  - reset-names: Must include the following entries:
    - dpaux
  - vdd-supply: phandle of a supply that powers the DisplayPort link

Example:

/ {
 ...

 host1x {
  compatible = "nvidia,tegra20-host1x", "simple-bus";
  reg = <0x50000000 0x00024000>;
  interrupts = <0 65 0x04   /* mpcore syncpt */
         0 67 0x04>; /* mpcore general */
  clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  resets = <&tegra_car 28>;
  reset-names = "host1x";

  #address-cells = <1>;
  #size-cells = <1>;

  ranges = <0x54000000 0x54000000 0x04000000>;

  mpe {
   compatible = "nvidia,tegra20-mpe";
   reg = <0x54040000 0x00040000>;
   interrupts = <0 68 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_MPE>;
   resets = <&tegra_car 60>;
   reset-names = "mpe";
  };

  vi {
   compatible = "nvidia,tegra20-vi";
   reg = <0x54080000 0x00040000>;
   interrupts = <0 69 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_VI>;
   resets = <&tegra_car 100>;
   reset-names = "vi";
  };

  epp {
   compatible = "nvidia,tegra20-epp";
   reg = <0x540c0000 0x00040000>;
   interrupts = <0 70 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_EPP>;
   resets = <&tegra_car 19>;
   reset-names = "epp";
  };

  isp {
   compatible = "nvidia,tegra20-isp";
   reg = <0x54100000 0x00040000>;
   interrupts = <0 71 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_ISP>;
   resets = <&tegra_car 23>;
   reset-names = "isp";
  };

  gr2d {
   compatible = "nvidia,tegra20-gr2d";
   reg = <0x54140000 0x00040000>;
   interrupts = <0 72 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_GR2D>;
   resets = <&tegra_car 21>;
   reset-names = "2d";
  };

  gr3d {
   compatible = "nvidia,tegra20-gr3d";
   reg = <0x54180000 0x00040000>;
   clocks = <&tegra_car TEGRA20_CLK_GR3D>;
   resets = <&tegra_car 24>;
   reset-names = "3d";
  };

  dc@54200000 {
   compatible = "nvidia,tegra20-dc";
   reg = <0x54200000 0x00040000>;
   interrupts = <0 73 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_DISP1>,
     <&tegra_car TEGRA20_CLK_PLL_P>;
   clock-names = "dc", "parent";
   resets = <&tegra_car 27>;
   reset-names = "dc";

   rgb {
    status = "disabled";
   };
  };

  dc@54240000 {
   compatible = "nvidia,tegra20-dc";
   reg = <0x54240000 0x00040000>;
   interrupts = <0 74 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_DISP2>,
     <&tegra_car TEGRA20_CLK_PLL_P>;
   clock-names = "dc", "parent";
   resets = <&tegra_car 26>;
   reset-names = "dc";

   rgb {
    status = "disabled";
   };
  };

  hdmi {
   compatible = "nvidia,tegra20-hdmi";
   reg = <0x54280000 0x00040000>;
   interrupts = <0 75 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_HDMI>,
     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
   clock-names = "hdmi", "parent";
   resets = <&tegra_car 51>;
   reset-names = "hdmi";
   status = "disabled";
  };

  tvo {
   compatible = "nvidia,tegra20-tvo";
   reg = <0x542c0000 0x00040000>;
   interrupts = <0 76 0x04>;
   clocks = <&tegra_car TEGRA20_CLK_TVO>;
   status = "disabled";
  };

  dsi {
   compatible = "nvidia,tegra20-dsi";
   reg = <0x54300000 0x00040000>;
   clocks = <&tegra_car TEGRA20_CLK_DSI>,
     <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
   clock-names = "dsi", "parent";
   resets = <&tegra_car 48>;
   reset-names = "dsi";
   status = "disabled";
  };
 };

 ...
};
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2016年4月1日 星期五

山口元素

Deck: RB {w}{b}{r}
CreaturesSpellsLandsSideboard
1Dragonmaster Outcast {R}1Skin Invasion {R}1Battlefield Forge 2Ruinous Path {1}{B}{B}
1Sanitarium Skeleton {B}4Sinister Concoction {B}2Caves of Koilos 1Infinite Obliteration {1}{B}{B}
1Rancid Rats {1}{B}1Visions of Brutality {1}{B}1Crumbling Vestige 3Flaying Tendrils {1}{B}{B}
4Crater Elemental {2}{R}2Warping Wail {1}{C}4Evolving Wilds 2Self-Inflicted Wound {1}{B}
1Graveblade Marauder {2}{B}1Dazzling Reflection {1}{W}2Mirrorpool 1Virulent Plague {2}{B}
1Pitiless Horde {2}{B}2Merciless Resolve {2}{B}1Mortuary Mire 1Shamble Back {B}
1Accursed Witch {3}{B}1Pick the Brain {2}{B}2Mountain 1Chandra, Flamecaller {4}{R}{R}
3Thought-Knot Seer {3}{C}1Gravepurge {2}{B}2Plains 3Rending Volley {R}
2Reality Smasher {4}{C}2Languish {2}{B}{B}1Shambling Vent 1Ultimate Price {1}{B}
1Rakshasa Gravecaller {4}{B}4Smoldering Marsh 1Behold the Beyond {5}{B}{B}
2Sidisi, Undead Vizier {3}{B}{B}2Swamp 2Burn from Within {X}{R}
1Dragonlord Kolaghan {4}{B}{R}3Warped Landscape 4Anguished Unmaking {1}{W}{B}
1Wastes 2Vessel of Malignity {1}{B}
19cards15cards26cards24cards
 Display deck statistics
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